Sandy Saper joined Ready in 2020 as ASIC & FPGA Design Manager. Sandy brings over 20 years of experience in managing complex SOC’s for wireless, communications & automotive applications. His experience encompasses all aspects of the SOC development cycle from requirements, specifications, architecture, design, verification, circuit, backend and silicon validation. Sandy has a proven record of managing multidisciplinary development teams and execution of projects efficiently and effectively. Prior to joining Ready Sandy was Director of Engineering at Verisense, before that he was R&D Department Manager at Freescale Semiconductors. Sandy holds a B.Sc. in Electrical Engineering from the Technion Institute of Technology, in Haifa, Israel